Sampler circuits are circuits that ascertain the state of an applied signal by rapidly quantizing, or sampling, the signal and processing the samples as being representative of one or more features of the sampled signal. In some applications, sampler circuits may only be required to ascertain specific features of an applied signal, such as the timing of state transitions for a periodic signal such as a digital clock signal.
A Phase Locked Loop (PLL) is a well-known circuit for deriving a steady (sometimes changeable or tunable) high frequency output signal. PLL are widely used in communication circuits, such as for generating carrier and local oscillator frequency signals for the modulation and demodulation of radio communication signals. PLLs compare a divided Radio Frequency (RF) signal with a reference clock to achieve phase lock, thus stabilizing the frequency of the undivided RF output. FIG. 11 depicts a functional block diagram of a conventional analog PLL. A Phase Frequency Detector (PFD) 12 compares the phases of a reference clock from a precision source 14, such as a crystal oscillator, to a feedback signal from a divider 16. The divider 16 divides down an RF output signal to the PLL operating frequency. The PFD 12 converts the phase difference between the reference clock and the divided RF signal into a control voltage level output. The PDF 12 output is low-pass filtered by a filter 18, and the control voltage is input to a Voltage Controlled Oscillator (VCO) 19 that changes the frequency of an RF output signal in response to the control voltage level.
Recently, digital PLL architectures have evolved, in which the phase difference is measured in a quantized fashion and converted into a digital control code for a Digitally Controlled Oscillator (DCO). A digital phase detector measures the phase difference. Prior art digital phase detectors are susceptible to meta-stability problems due to the asynchronous relationship between the sampling clock and the sampled reference clock. Furthermore, known digital phase detectors are not very sensitive, and they suffer from hysteresis and dead-zone/dead-time, due to regenerative gain.